1. Field of the Invention
This invention relates generally to semiconductor devices, and more particularly, to a method and apparatus for reducing leakage current in a transfer transistor in a back bias voltage generator for a DRAM semiconductor device.
2. Description of the Related Art
A DRAM semiconductor device has a plurality of memory cells for storing information and peripheral circuits for reading and writing data to the memory cells. During operation of a DRAM semiconductor device, leakage current can be generated between the memory cells, the peripheral circuits, and the substrate of the DRAM device. To prevent leakage current, a back bias generator is used to apply a back bias to the substrate.
FIG. 1 is a circuit diagram of a conventional back bias generator for a DRAM semiconductor device. Referring to FIG. 1, the conventional back bias generator 5 includes an oscillator 11, a power-supply voltage generator 13, a NAND gate 15, a pumping capacitor (Cp), a clamp transistor 17 and a PMOS transfer transistor 19.
The operation of the back bias generator for a semiconductor device 5 will now be explained. When the power-supply voltage generator 13 begins generating a power-supply voltage Vcc, the oscillator 11 generates a clock signal. In response to the clock signal, the pumping capacitor Cp generates a negative pumping voltage. The negative pumping voltage is generated as a back bias V.sub.BB through the transfer transistor 19.
FIG. 2 is a sectional view of a DRAM semiconductor device 7 showing the structure of transfer transistor 19. Referring to FIG. 2, an N well 23 is formed in a P-substrate 21. A source 25 and a drain 27 for the transfer transistor 19 are formed in the N well 23.
As DRAM memory cells become more highly integrated, the design rule is reduced and the level of a power-supply voltage Vcc is lowered. Accordingly, the power-supply capacity of a back bias generator becomes insufficient. Therefore, to improve the power supply capacity of the back bias generator for a semiconductor device, the PMOS transistor used as the transfer transistor shown in FIG. 1 must be replaced with an NMOS transistor. This is because an NMOS transistor has a threshold voltage that is lower than that of a PMOS transistor while having a greater driving capacity.
FIG. 3 is a circuit diagram of a conventional back bias generator 35 that utilizes an NMOS transistor as a transfer transistor 39. The power supply capacity of the back bias generator 35 of FIG. 3 is greater than that of the circuit of FIG. 1. However, when the circuit shown in FIG. 3 is utilized in a DRAM semiconductor device having a triple-well structure, as shown in FIG. 4, a leakage current il is generated between the transfer transistor 39 and the P-substrate 21 because a PNP structure 43 is formed between the transfer transistor 39 and the P-substrate 21. Reference numeral 30 designates the gate of transfer transistor 39.
Referring to FIGS. 3 and 4, the negative pumping voltage generated by the pumping capacitor Cp does not pass through the transfer transistor 39 but is discharged to the P-substrate 21 through the PNP structure 43. This reduces the power supply capacity of the back bias generator 35 shown in FIG. 3. Accordingly, leakage current is generated between memory cells (not shown) that utilize the back bias V.sub.BB. This phenomenon is serious at power-up time. The leakage current deteriorates the refresh characteristics of the DRAM semiconductor device. Also, instability of the back bias level due to noise in the DRAM reduces the response time of the device.
Accordingly, a need remains for an improved scheme for generating a back bias signal in a semiconductor device.